Aaron Barnes

I’m a PhD candidate at Purdue University in the School of Electrical and Computer Engineering advised by Professor Tim Rogers within the AALP research group. Recently I was an intern at AMD Research where I investigated microarchitectectural features to improve the performance of Bounding Volume Hierarchy (BVH) construction algorithms used for ray tracing on the next generation of GPUs.

My research interests broadly span parallel processing architectures and improving the programmability of hardware accelerators. Specifically, my work has studied the core architecture changes necessary to drive power and performance improvements across the increasingly diverse set of applications targeted for GPUs. Recently my work has focused on improving ray tracing hardware acceleration units on GPUs and expanding their utility to domains beyond traditional graphics applications. I also have an ongoing interest in expanding and improving cycle-level architecture simulators like Accel-Sim and gem5.

Previously I have worked on product teams at Intel, Arm, and Collins Aerospace doing performance characterization, pre-silicon verification, and Printed Circuit Board (PCB) design.