Aaron Barnes

I’m a Research Scientist at Meta on the ML Systems HW/SW Codesign team, where I work on custom silicon systems like the Meta Training and Inference Accelerator (MTIA). I completed my PhD in Electrical and Computer Engineering at Purdue University under the supervision of Professor Tim Rogers within the AALP research group, focusing on GPU microarchitecture.

My research interests broadly span parallel processing architectures and improving the programmability of hardware accelerators. My PhD thesis Improving the Utilization and Performance of Specialized GPU Cores, studied the impact of core partitioning on warp-specialized workloads and explored expanding the utility of ray tracing hardware acceleration units beyond traditional graphics applications. I also have an ongoing interest in expanding and improving cycle-level architecture simulators like Accel-Sim and gem5.

Previously, I worked as a Research Scientist Intern at Meta on the SoC Creations team in Reality Labs, where I worked on performance models for AR/VR silicon. I have also worked as an intern at AMD Research, where I investigated microarchitectectural features to improve the performance of Bounding Volume Hierarchy (BVH) construction algorithms used for ray tracing on GPUs. Prior to that, I worked on product teams at Intel, Arm, and Collins Aerospace doing performance characterization, pre-silicon verification, and Printed Circuit Board (PCB) design.